1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a gate with a metal layer.
2. Description of the Related Art
Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.
One of the most widespread technologies is the complementary metal-oxidesemiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs and N-channel FETs, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials, such as, for example, dopant atoms or ions, may be introduced into the original semiconductor layer.
When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices.
Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages such as dopant ion implantation, source and drain region formation and substrate silicidation are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology.
For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level.
In the gate-first HKMG approach, a thin film of a silicon/germanium (SiGe) alloy is deposited on the surface of the silicon layer in order to adjust the transistor threshold voltage to a desired level. Since a portion of this thin film is included in the channel region of the FET, this SiGe thin film is also commonly referred to as “channel SiGe.”
Since epitaxial SiGe epitaxially grown on silicon experiences a compressive stress, SiGe alloys may also be used to introduce a desired stress component into the channel region of a P-channel FET. This is a desirable effect since the mobility of holes in the channel region of a P-channel FET is known to increase when the channel region experiences a compressive stress. Thus, trenches may be formed in portions of the source and drain regions of a FET adjacent to the channel region. An SiGe alloy may be subsequently epitaxially grown in the trenches. This SiGe is also commonly referred to as “embedded SiGe.”
Furthermore, in the HKMG technology, a thin “work function metal” layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage may thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). A work function metal, such as, for example, aluminum, may also be included in the gate metal layer.
Since the gate material formed on top of the gate metal layer is usually a semiconductor, for example poly-Si, a Schottky barrier is established at the interface between the gate metal layer and the gate semiconductor material. This undesirably degrades the AC performance by limiting the circuit switching speed.
FIGS. 1a-1c show some aspects of a transistor manufacturing flow according to the known gate-first HKMG approach.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor structure 100 in an advanced manufacturing stage. The semiconductor structure 100 has been obtained after forming insulation regions 102b in a semiconductor layer 102. Insulation regions 102b may have been formed as shallow trench isolations. The semiconductor layer 102, typically comprising monocrystalline silicon, is formed on a substrate 101, which may be comprised of any appropriate carrier.
Active regions 102a are subsequently formed in the semiconductor layer 102. This may comprise performing one or more well implantations. Active regions are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience of display, a single active region 102a is illustrated, which is laterally limited by insulation regions 102b. 
FIG. 1a shows that a FET 150 has been formed after defining the active region 102a. In the gate-first HKMG, a gate structure 160 is formed on the upper surface of the active region 102a. Although not shown, a thin channel SiGe film may have been deposited on the surface of the active region 102a before forming the gate structure 160.
The gate structure 160 is formed by sequentially stacking layers of different materials, which are subsequently patterned so as to obtain the desired gate structure size and dimensions. The stack making up the gate structure 160 comprises: insulation layer 161 formed on the surface of the active region 102a; gate metal layer 164; gate material 162; and a cap layer (not shown) formed adjacent to the gate material 162 and exposing an upper surface to the outside. The gate stack is usually laterally delimited by a spacer structure 163, which may be advantageously used as an implantation mask in subsequent manufacturing stages.
The insulation layer 161, formed on the surface of the active region 102a, comprises a high-k material. The gate metal layer 164 is formed between the insulation layer 161 and the gate material 162 so as to adjust the transistor threshold voltage. The gate material 162, formed directly on the upper surface of the gate metal layer 164, typically comprises a semiconductor, such as poly Si. The cap layer is formed at the top of the gate stack and usually is comprised of an insulating, relatively tough material such as, for example, silicon nitride (Si3N4).
Where needed, embedded SiGe alloy layers may be formed in the active region 102a after forming the gate structure 160.
Thereafter, several implantations are carried out in order to define source and drain regions 151 of the transistor 150. The implantations may comprise halo/extension implants, giving rise to extension regions 151e and halo regions (not shown) in the active region 102a. After performing halo/extension implantations, the spacer structure 160 may be broadened and an additional series of implantations may be carried out in order to form deep regions 151d of the source and drain regions 151.
According to the conventional manufacturing flow, the insulating cap layer is removed from the top of the gate structure 160 before performing these implantations. Typically, the cap layer is removed after forming the gate structure 160 and before performing the halo/extension implantations. After removing the cap layer, the gate structure 160 exposes the gate material 162 to the outside, as shown in FIG. 1a. 
An annealing step follows the series of implantations defining source and drain regions 151. Annealing is performed in order to activate the implanted dopant ions and to allow the crystalline structure to recover from implantation damage.
After the annealing step, a metal silicide layer is formed in order to decrease the contact resistance to the electrodes of the transistor 150. The process of metal silicide formation is schematically illustrated in FIGS. 1b and 1c. 
As shown in FIG. 1b, a refractory metal layer 108 is deposited onto the exposed face of the semiconductor structure 100. The refractory metal layer 108 may comprise, for example, a metal, such as nickel, titanium, cobalt and the like. Preferably, the refractory metal layer 108 comprises nickel. The refractory metal layer 108 may also comprise platinum, which, in some cases, may promote a more homogeneous formation of nickel monosilicide.
A heat treatment is then applied to the semiconductor structure 100 in order to promote a chemical reaction between the metal atoms of the layer 108 and the silicon atoms of the exposed surface of the semiconductor structure 100.
FIG. 1c shows that, as a result of the heat treatment, nickel silicide regions 153 and 162a are formed, that substantially comprise low-resistivity nickel monosilicide. More specifically, the metal silicide layer 153 has formed partly in and partly on top of the active region 102a, thus forming an interface with the source and drain regions 151. On the other hand, the metal silicide layer 162a has formed on top of the gate structure 160, thus forming an interface with the gate material 162 exposed before the deposition of the metal layer 108. It should be noted that the silicon material contained in the sidewall spacer structure 163 and the insulating regions 102b does not substantially take part in the chemical reaction induced during the heat treatment process, as it is present in those features only as a thermally stable silicon dioxide and/or silicon nitride material.
As said above, the transistor resulting from the above-described manufacturing flow is affected by the drawback of the Schottky barrier forming at the interface between the gate metal layer 164 and the gate material 162. In order to get rid of this Schottky barrier, it would be convenient to form a metal silicide layer 162a of a thickness sufficient for directly forming an interface with the gate metal layer 164.
One method of achieving this goal is forming so-called “fully silicided” gates, wherein the metal silicide layer 162a totally replaces the gate material 162 so as to directly contact the gate metal layer 164. An example of a method of forming a fully silicided gate structure may be found in U.S. Pat. No. 6,821,887. In this application, the height of the gate structure is appropriately chosen so as to permit the reaction of all gate material with the refractive metal during the silicidation process described above.
However, the methods of forming a fully silicided gate known from the prior art use the same silicidation step for forming the metal silicide layer 153 on the source/drain regions and the metal silicide layer 162a on top of the gate, as described above. Thus, the thickness of the gate metal silicide layer 162a is correlated to the thickness of the source/drain metal silicide layer 153. This is a serious limitation, since the thickness of the source/drain metal silicide layer 153 may not be increased beyond a maximum. In general, the thickness of the source/drain metal silicide layer 153 must be considerably smaller than the thickness of the semiconductor layer 102. This problem becomes more and more urgent as the typical device sizes decrease, since reducing, for example, the gate length also requires a corresponding scaling of source and drain regions 151 in the vertical direction.
By using known methods, it is, thus, particularly difficult to obtain a fully silicided gate while maintaining the thickness of the source/drain metal silicide layer at a sufficiently low value. Therefore, a need arises for an improved transistor manufacturing method permitting formation of a source/drain metal silicide layer and a gate metal/silicide layer of desired thicknesses.